distortos  v0.4.0
object-oriented C++ RTOS for microcontrollers
distortosConfiguration.h
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1 
11 #ifndef INCLUDE_DISTORTOS_DISTORTOSCONFIGURATION_H_
12 #define INCLUDE_DISTORTOS_DISTORTOSCONFIGURATION_H_
13 
14 #define CONFIG_CHIP_STM32
15 #undef CONFIG_CHIP_STM32F0
16 #undef CONFIG_CHIP_STM32F1
17 #define CONFIG_CHIP_STM32F4
18 #undef CONFIG_CHIP_STM32F7
19 #undef CONFIG_BOARD_CUSTOM
20 #undef CONFIG_BOARD_32F429IDISCOVERY
21 #undef CONFIG_BOARD_NUCLEO_F401RE
22 #undef CONFIG_BOARD_NUCLEO_F429ZI
23 #define CONFIG_BOARD_STM32F4DISCOVERY
24 #define CONFIG_BOARD_INCLUDES "source/board/STM32/STM32F4/STM32F4DISCOVERY/include"
25 #define CONFIG_BOARD "STM32F4DISCOVERY"
26 #undef CONFIG_CHIP_STM32F4_VDD_MV_CONFIGURABLE
27 #define CONFIG_CHIP_STM32F4_VDD_MV_DEFAULT 3000
28 #undef CONFIG_CHIP_STM32F4_RCC_HSE_CLOCK_BYPASS_CONFIGURABLE
29 #undef CONFIG_CHIP_STM32F4_RCC_HSE_CLOCK_BYPASS_DEFAULT
30 #undef CONFIG_CHIP_STM32F4_RCC_HSE_FREQUENCY_CONFIGURABLE
31 #define CONFIG_CHIP_STM32F4_RCC_HSE_FREQUENCY_DEFAULT 8000000
32 #define CONFIG_BOARD_BUTTONS_ENABLE
33 #define CONFIG_BOARD_LEDS_ENABLE
34 #define CONFIG_BOARD_HAS_BUTTONS
35 #define CONFIG_BOARD_HAS_LEDS
36 #define CONFIG_CHIP_ROM_SIZE 1048576
37 #define CONFIG_CHIP_ROM_ADDRESS 0x08000000
38 #define CONFIG_CHIP "STM32F407VG"
39 #define CONFIG_CHIP_INCLUDES "source/chip/STM32/include source/chip/STM32/STM32F4/include source/chip/STM32/peripherals/GPIOv2/include source/chip/STM32/peripherals/SPIv1/include source/chip/STM32/peripherals/USARTv1/include external/CMSIS-STM32F4 external/CMSIS"
40 #define CONFIG_CHIP_STM32F4_VDD_MV 3000
41 #define CONFIG_CHIP_STM32F4_STANDARD_CLOCK_CONFIGURATION_ENABLE
42 #define CONFIG_CHIP_STM32F4_PWR_VOLTAGE_SCALE_MODE 1
43 #define CONFIG_CHIP_STM32F4_RCC_HSE_ENABLE
44 #undef CONFIG_CHIP_STM32F4_RCC_HSE_CLOCK_BYPASS
45 #define CONFIG_CHIP_STM32F4_RCC_HSE_FREQUENCY 8000000
46 #define CONFIG_CHIP_STM32F4_RCC_PLL_ENABLE
47 #undef CONFIG_CHIP_STM32F4_RCC_PLLSRC_HSI
48 #define CONFIG_CHIP_STM32F4_RCC_PLLSRC_HSE
49 #define CONFIG_CHIP_STM32F4_RCC_PLLM 4
50 #define CONFIG_CHIP_STM32F4_RCC_PLLN 168
51 #define CONFIG_CHIP_STM32F4_RCC_PLLP_DIV2
52 #undef CONFIG_CHIP_STM32F4_RCC_PLLP_DIV4
53 #undef CONFIG_CHIP_STM32F4_RCC_PLLP_DIV6
54 #undef CONFIG_CHIP_STM32F4_RCC_PLLP_DIV8
55 #define CONFIG_CHIP_STM32F4_RCC_PLLQ 7
56 #undef CONFIG_CHIP_STM32F4_RCC_SYSCLK_HSI
57 #undef CONFIG_CHIP_STM32F4_RCC_SYSCLK_HSE
58 #define CONFIG_CHIP_STM32F4_RCC_SYSCLK_PLL
59 #define CONFIG_CHIP_STM32F4_RCC_AHB_DIV1
60 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV2
61 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV4
62 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV8
63 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV16
64 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV64
65 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV128
66 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV256
67 #undef CONFIG_CHIP_STM32F4_RCC_AHB_DIV512
68 #undef CONFIG_CHIP_STM32F4_RCC_APB1_DIV1
69 #undef CONFIG_CHIP_STM32F4_RCC_APB1_DIV2
70 #define CONFIG_CHIP_STM32F4_RCC_APB1_DIV4
71 #undef CONFIG_CHIP_STM32F4_RCC_APB1_DIV8
72 #undef CONFIG_CHIP_STM32F4_RCC_APB1_DIV16
73 #undef CONFIG_CHIP_STM32F4_RCC_APB2_DIV1
74 #define CONFIG_CHIP_STM32F4_RCC_APB2_DIV2
75 #undef CONFIG_CHIP_STM32F4_RCC_APB2_DIV4
76 #undef CONFIG_CHIP_STM32F4_RCC_APB2_DIV8
77 #undef CONFIG_CHIP_STM32F4_RCC_APB2_DIV16
78 #undef CONFIG_CHIP_STM32F4_FLASH_PREFETCH_ENABLE
79 #define CONFIG_CHIP_STM32F4_FLASH_DATA_CACHE_ENABLE
80 #define CONFIG_CHIP_STM32F4_FLASH_INSTRUCTION_CACHE_ENABLE
81 #undef CONFIG_CHIP_STM32F4_UNIFY_NONE
82 #define CONFIG_CHIP_STM32F4_UNIFY_SRAM1_SRAM2
83 #define CONFIG_CHIP_STM32F40
84 #undef CONFIG_CHIP_STM32F401
85 #undef CONFIG_CHIP_STM32F401C
86 #undef CONFIG_CHIP_STM32F401CB
87 #undef CONFIG_CHIP_STM32F401CC
88 #undef CONFIG_CHIP_STM32F401CD
89 #undef CONFIG_CHIP_STM32F401CE
90 #undef CONFIG_CHIP_STM32F401R
91 #undef CONFIG_CHIP_STM32F401RB
92 #undef CONFIG_CHIP_STM32F401RC
93 #undef CONFIG_CHIP_STM32F401RD
94 #undef CONFIG_CHIP_STM32F401RE
95 #undef CONFIG_CHIP_STM32F401V
96 #undef CONFIG_CHIP_STM32F401VB
97 #undef CONFIG_CHIP_STM32F401VC
98 #undef CONFIG_CHIP_STM32F401VD
99 #undef CONFIG_CHIP_STM32F401VE
100 #undef CONFIG_CHIP_STM32F405
101 #undef CONFIG_CHIP_STM32F405O
102 #undef CONFIG_CHIP_STM32F405OE
103 #undef CONFIG_CHIP_STM32F405OG
104 #undef CONFIG_CHIP_STM32F405R
105 #undef CONFIG_CHIP_STM32F405RG
106 #undef CONFIG_CHIP_STM32F405V
107 #undef CONFIG_CHIP_STM32F405VG
108 #undef CONFIG_CHIP_STM32F405Z
109 #undef CONFIG_CHIP_STM32F405ZG
110 #define CONFIG_CHIP_STM32F407
111 #undef CONFIG_CHIP_STM32F407I
112 #undef CONFIG_CHIP_STM32F407IE
113 #undef CONFIG_CHIP_STM32F407IG
114 #define CONFIG_CHIP_STM32F407V
115 #undef CONFIG_CHIP_STM32F407VE
116 #define CONFIG_CHIP_STM32F407VG
117 #undef CONFIG_CHIP_STM32F407Z
118 #undef CONFIG_CHIP_STM32F407ZE
119 #undef CONFIG_CHIP_STM32F407ZG
120 #undef CONFIG_CHIP_STM32F41
121 #undef CONFIG_CHIP_STM32F410
122 #undef CONFIG_CHIP_STM32F410C
123 #undef CONFIG_CHIP_STM32F410C8
124 #undef CONFIG_CHIP_STM32F410CB
125 #undef CONFIG_CHIP_STM32F410R
126 #undef CONFIG_CHIP_STM32F410R8
127 #undef CONFIG_CHIP_STM32F410RB
128 #undef CONFIG_CHIP_STM32F410T
129 #undef CONFIG_CHIP_STM32F410T8
130 #undef CONFIG_CHIP_STM32F410TB
131 #undef CONFIG_CHIP_STM32F411
132 #undef CONFIG_CHIP_STM32F411C
133 #undef CONFIG_CHIP_STM32F411CC
134 #undef CONFIG_CHIP_STM32F411CE
135 #undef CONFIG_CHIP_STM32F411R
136 #undef CONFIG_CHIP_STM32F411RC
137 #undef CONFIG_CHIP_STM32F411RE
138 #undef CONFIG_CHIP_STM32F411V
139 #undef CONFIG_CHIP_STM32F411VC
140 #undef CONFIG_CHIP_STM32F411VE
141 #undef CONFIG_CHIP_STM32F412
142 #undef CONFIG_CHIP_STM32F412C
143 #undef CONFIG_CHIP_STM32F412CE
144 #undef CONFIG_CHIP_STM32F412CG
145 #undef CONFIG_CHIP_STM32F412R
146 #undef CONFIG_CHIP_STM32F412RE
147 #undef CONFIG_CHIP_STM32F412RG
148 #undef CONFIG_CHIP_STM32F412V
149 #undef CONFIG_CHIP_STM32F412VE
150 #undef CONFIG_CHIP_STM32F412VG
151 #undef CONFIG_CHIP_STM32F412Z
152 #undef CONFIG_CHIP_STM32F412ZE
153 #undef CONFIG_CHIP_STM32F412ZG
154 #undef CONFIG_CHIP_STM32F413
155 #undef CONFIG_CHIP_STM32F413C
156 #undef CONFIG_CHIP_STM32F413CG
157 #undef CONFIG_CHIP_STM32F413CH
158 #undef CONFIG_CHIP_STM32F413M
159 #undef CONFIG_CHIP_STM32F413MG
160 #undef CONFIG_CHIP_STM32F413MH
161 #undef CONFIG_CHIP_STM32F413R
162 #undef CONFIG_CHIP_STM32F413RG
163 #undef CONFIG_CHIP_STM32F413RH
164 #undef CONFIG_CHIP_STM32F413V
165 #undef CONFIG_CHIP_STM32F413VG
166 #undef CONFIG_CHIP_STM32F413VH
167 #undef CONFIG_CHIP_STM32F413Z
168 #undef CONFIG_CHIP_STM32F413ZG
169 #undef CONFIG_CHIP_STM32F413ZH
170 #undef CONFIG_CHIP_STM32F415
171 #undef CONFIG_CHIP_STM32F415O
172 #undef CONFIG_CHIP_STM32F415OG
173 #undef CONFIG_CHIP_STM32F415R
174 #undef CONFIG_CHIP_STM32F415RG
175 #undef CONFIG_CHIP_STM32F415V
176 #undef CONFIG_CHIP_STM32F415VG
177 #undef CONFIG_CHIP_STM32F415Z
178 #undef CONFIG_CHIP_STM32F415ZG
179 #undef CONFIG_CHIP_STM32F417
180 #undef CONFIG_CHIP_STM32F417I
181 #undef CONFIG_CHIP_STM32F417IE
182 #undef CONFIG_CHIP_STM32F417IG
183 #undef CONFIG_CHIP_STM32F417V
184 #undef CONFIG_CHIP_STM32F417VE
185 #undef CONFIG_CHIP_STM32F417VG
186 #undef CONFIG_CHIP_STM32F417Z
187 #undef CONFIG_CHIP_STM32F417ZE
188 #undef CONFIG_CHIP_STM32F417ZG
189 #undef CONFIG_CHIP_STM32F42
190 #undef CONFIG_CHIP_STM32F423
191 #undef CONFIG_CHIP_STM32F423C
192 #undef CONFIG_CHIP_STM32F423CH
193 #undef CONFIG_CHIP_STM32F423M
194 #undef CONFIG_CHIP_STM32F423MH
195 #undef CONFIG_CHIP_STM32F423R
196 #undef CONFIG_CHIP_STM32F423RH
197 #undef CONFIG_CHIP_STM32F423V
198 #undef CONFIG_CHIP_STM32F423VH
199 #undef CONFIG_CHIP_STM32F423Z
200 #undef CONFIG_CHIP_STM32F423ZH
201 #undef CONFIG_CHIP_STM32F427
202 #undef CONFIG_CHIP_STM32F427A
203 #undef CONFIG_CHIP_STM32F427AG
204 #undef CONFIG_CHIP_STM32F427AI
205 #undef CONFIG_CHIP_STM32F427I
206 #undef CONFIG_CHIP_STM32F427IG
207 #undef CONFIG_CHIP_STM32F427II
208 #undef CONFIG_CHIP_STM32F427V
209 #undef CONFIG_CHIP_STM32F427VG
210 #undef CONFIG_CHIP_STM32F427VI
211 #undef CONFIG_CHIP_STM32F427Z
212 #undef CONFIG_CHIP_STM32F427ZG
213 #undef CONFIG_CHIP_STM32F427ZI
214 #undef CONFIG_CHIP_STM32F429
215 #undef CONFIG_CHIP_STM32F429A
216 #undef CONFIG_CHIP_STM32F429AG
217 #undef CONFIG_CHIP_STM32F429AI
218 #undef CONFIG_CHIP_STM32F429B
219 #undef CONFIG_CHIP_STM32F429BE
220 #undef CONFIG_CHIP_STM32F429BG
221 #undef CONFIG_CHIP_STM32F429BI
222 #undef CONFIG_CHIP_STM32F429I
223 #undef CONFIG_CHIP_STM32F429IE
224 #undef CONFIG_CHIP_STM32F429IG
225 #undef CONFIG_CHIP_STM32F429II
226 #undef CONFIG_CHIP_STM32F429N
227 #undef CONFIG_CHIP_STM32F429NE
228 #undef CONFIG_CHIP_STM32F429NG
229 #undef CONFIG_CHIP_STM32F429NI
230 #undef CONFIG_CHIP_STM32F429V
231 #undef CONFIG_CHIP_STM32F429VE
232 #undef CONFIG_CHIP_STM32F429VG
233 #undef CONFIG_CHIP_STM32F429VI
234 #undef CONFIG_CHIP_STM32F429Z
235 #undef CONFIG_CHIP_STM32F429ZE
236 #undef CONFIG_CHIP_STM32F429ZG
237 #undef CONFIG_CHIP_STM32F429ZI
238 #undef CONFIG_CHIP_STM32F43
239 #undef CONFIG_CHIP_STM32F437
240 #undef CONFIG_CHIP_STM32F437A
241 #undef CONFIG_CHIP_STM32F437AI
242 #undef CONFIG_CHIP_STM32F437I
243 #undef CONFIG_CHIP_STM32F437IG
244 #undef CONFIG_CHIP_STM32F437II
245 #undef CONFIG_CHIP_STM32F437V
246 #undef CONFIG_CHIP_STM32F437VG
247 #undef CONFIG_CHIP_STM32F437VI
248 #undef CONFIG_CHIP_STM32F437Z
249 #undef CONFIG_CHIP_STM32F437ZG
250 #undef CONFIG_CHIP_STM32F437ZI
251 #undef CONFIG_CHIP_STM32F439
252 #undef CONFIG_CHIP_STM32F439A
253 #undef CONFIG_CHIP_STM32F439AI
254 #undef CONFIG_CHIP_STM32F439B
255 #undef CONFIG_CHIP_STM32F439BG
256 #undef CONFIG_CHIP_STM32F439BI
257 #undef CONFIG_CHIP_STM32F439I
258 #undef CONFIG_CHIP_STM32F439IG
259 #undef CONFIG_CHIP_STM32F439II
260 #undef CONFIG_CHIP_STM32F439N
261 #undef CONFIG_CHIP_STM32F439NG
262 #undef CONFIG_CHIP_STM32F439NI
263 #undef CONFIG_CHIP_STM32F439V
264 #undef CONFIG_CHIP_STM32F439VG
265 #undef CONFIG_CHIP_STM32F439VI
266 #undef CONFIG_CHIP_STM32F439Z
267 #undef CONFIG_CHIP_STM32F439ZG
268 #undef CONFIG_CHIP_STM32F439ZI
269 #undef CONFIG_CHIP_STM32F44
270 #undef CONFIG_CHIP_STM32F446
271 #undef CONFIG_CHIP_STM32F446M
272 #undef CONFIG_CHIP_STM32F446MC
273 #undef CONFIG_CHIP_STM32F446ME
274 #undef CONFIG_CHIP_STM32F446R
275 #undef CONFIG_CHIP_STM32F446RC
276 #undef CONFIG_CHIP_STM32F446RE
277 #undef CONFIG_CHIP_STM32F446V
278 #undef CONFIG_CHIP_STM32F446VC
279 #undef CONFIG_CHIP_STM32F446VE
280 #undef CONFIG_CHIP_STM32F446Z
281 #undef CONFIG_CHIP_STM32F446ZC
282 #undef CONFIG_CHIP_STM32F446ZE
283 #undef CONFIG_CHIP_STM32F46
284 #undef CONFIG_CHIP_STM32F469
285 #undef CONFIG_CHIP_STM32F469A
286 #undef CONFIG_CHIP_STM32F469AE
287 #undef CONFIG_CHIP_STM32F469AG
288 #undef CONFIG_CHIP_STM32F469AI
289 #undef CONFIG_CHIP_STM32F469B
290 #undef CONFIG_CHIP_STM32F469BE
291 #undef CONFIG_CHIP_STM32F469BG
292 #undef CONFIG_CHIP_STM32F469BI
293 #undef CONFIG_CHIP_STM32F469I
294 #undef CONFIG_CHIP_STM32F469IE
295 #undef CONFIG_CHIP_STM32F469IG
296 #undef CONFIG_CHIP_STM32F469II
297 #undef CONFIG_CHIP_STM32F469N
298 #undef CONFIG_CHIP_STM32F469NE
299 #undef CONFIG_CHIP_STM32F469NG
300 #undef CONFIG_CHIP_STM32F469NI
301 #undef CONFIG_CHIP_STM32F469V
302 #undef CONFIG_CHIP_STM32F469VE
303 #undef CONFIG_CHIP_STM32F469VG
304 #undef CONFIG_CHIP_STM32F469VI
305 #undef CONFIG_CHIP_STM32F469Z
306 #undef CONFIG_CHIP_STM32F469ZE
307 #undef CONFIG_CHIP_STM32F469ZG
308 #undef CONFIG_CHIP_STM32F469ZI
309 #undef CONFIG_CHIP_STM32F47
310 #undef CONFIG_CHIP_STM32F479
311 #undef CONFIG_CHIP_STM32F479A
312 #undef CONFIG_CHIP_STM32F479AG
313 #undef CONFIG_CHIP_STM32F479AI
314 #undef CONFIG_CHIP_STM32F479B
315 #undef CONFIG_CHIP_STM32F479BG
316 #undef CONFIG_CHIP_STM32F479BI
317 #undef CONFIG_CHIP_STM32F479I
318 #undef CONFIG_CHIP_STM32F479IG
319 #undef CONFIG_CHIP_STM32F479II
320 #undef CONFIG_CHIP_STM32F479N
321 #undef CONFIG_CHIP_STM32F479NG
322 #undef CONFIG_CHIP_STM32F479NI
323 #undef CONFIG_CHIP_STM32F479V
324 #undef CONFIG_CHIP_STM32F479VG
325 #undef CONFIG_CHIP_STM32F479VI
326 #undef CONFIG_CHIP_STM32F479Z
327 #undef CONFIG_CHIP_STM32F479ZG
328 #undef CONFIG_CHIP_STM32F479ZI
329 #define CONFIG_CHIP_STM32F4_BKPSRAM_SIZE 4096
330 #define CONFIG_CHIP_STM32F4_BKPSRAM_ADDRESS 0x40024000
331 #define CONFIG_CHIP_STM32F4_CCM_SIZE 65536
332 #define CONFIG_CHIP_STM32F4_CCM_ADDRESS 0x10000000
333 #define CONFIG_CHIP_STM32F4_SRAM1_SIZE 114688
334 #define CONFIG_CHIP_STM32F4_SRAM1_ADDRESS 0x20000000
335 #define CONFIG_CHIP_STM32F4_SRAM2_SIZE 16384
336 #define CONFIG_CHIP_STM32F4_SRAM2_ADDRESS 0x2001c000
337 #define CONFIG_CHIP_STM32F4_SRAM3_SIZE 0
338 #define CONFIG_CHIP_STM32F4_RCC_HPRE 1
339 #define CONFIG_CHIP_STM32F4_RCC_PLLP 2
340 #define CONFIG_CHIP_STM32F4_RCC_PPRE1 4
341 #define CONFIG_CHIP_STM32F4_RCC_PPRE2 2
342 #define CONFIG_CHIP_STM32_GPIOV2_GPIOA_ENABLE
343 #undef CONFIG_CHIP_STM32_GPIOV2_GPIOB_ENABLE
344 #undef CONFIG_CHIP_STM32_GPIOV2_GPIOC_ENABLE
345 #define CONFIG_CHIP_STM32_GPIOV2_GPIOD_ENABLE
346 #undef CONFIG_CHIP_STM32_GPIOV2_GPIOE_ENABLE
347 #undef CONFIG_CHIP_STM32_GPIOV2_GPIOH_ENABLE
348 #define CONFIG_CHIP_STM32_GPIOV2_HAS_4_AF_BITS
349 #define CONFIG_CHIP_STM32_GPIOV2_HAS_HIGH_SPEED
350 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOA
351 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOB
352 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOC
353 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOD
354 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOE
355 #undef CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOF
356 #undef CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOG
357 #define CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOH
358 #undef CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOI
359 #undef CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOJ
360 #undef CONFIG_CHIP_STM32_GPIOV2_HAS_GPIOK
361 #undef CONFIG_CHIP_STM32_GPIOV1
362 #define CONFIG_CHIP_STM32_GPIOV2
363 #define CONFIG_CHIP_STM32_SPIV1
364 #undef CONFIG_CHIP_STM32_SPIV2
365 #define CONFIG_CHIP_STM32_USARTV1
366 #undef CONFIG_CHIP_STM32_USARTV2
367 #undef CONFIG_CHIP_STM32_SPIV1_SPI1_ENABLE
368 #undef CONFIG_CHIP_STM32_SPIV1_SPI2_ENABLE
369 #undef CONFIG_CHIP_STM32_SPIV1_SPI3_ENABLE
370 #define CONFIG_CHIP_STM32_SPIV1_HAS_SPI1
371 #define CONFIG_CHIP_STM32_SPIV1_HAS_SPI2
372 #define CONFIG_CHIP_STM32_SPIV1_HAS_SPI3
373 #undef CONFIG_CHIP_STM32_SPIV1_HAS_SPI4
374 #undef CONFIG_CHIP_STM32_SPIV1_HAS_SPI5
375 #undef CONFIG_CHIP_STM32_SPIV1_HAS_SPI6
376 #undef CONFIG_CHIP_STM32_USARTV1_USART1_ENABLE
377 #undef CONFIG_CHIP_STM32_USARTV1_USART2_ENABLE
378 #undef CONFIG_CHIP_STM32_USARTV1_USART3_ENABLE
379 #undef CONFIG_CHIP_STM32_USARTV1_UART4_ENABLE
380 #undef CONFIG_CHIP_STM32_USARTV1_UART5_ENABLE
381 #undef CONFIG_CHIP_STM32_USARTV1_USART6_ENABLE
382 #define CONFIG_CHIP_STM32_USARTV1_HAS_CR1_OVER8_BIT
383 #define CONFIG_CHIP_STM32_USARTV1_HAS_USART1
384 #define CONFIG_CHIP_STM32_USARTV1_HAS_USART2
385 #define CONFIG_CHIP_STM32_USARTV1_HAS_USART3
386 #define CONFIG_CHIP_STM32_USARTV1_HAS_UART4
387 #define CONFIG_CHIP_STM32_USARTV1_HAS_UART5
388 #define CONFIG_CHIP_STM32_USARTV1_HAS_USART6
389 #undef CONFIG_CHIP_STM32_USARTV1_HAS_UART7
390 #undef CONFIG_CHIP_STM32_USARTV1_HAS_UART8
391 #undef CONFIG_CHIP_STM32_USARTV1_HAS_UART9
392 #undef CONFIG_CHIP_STM32_USARTV1_HAS_UART10
393 #undef CONFIG_ARCHITECTURE_ARMV6_M
394 #define CONFIG_ARCHITECTURE_ARMV7_M
395 #define CONFIG_ARCHITECTURE_STACK_ALIGNMENT 8
396 #define CONFIG_TOOLCHAIN_PREFIX "arm-none-eabi-"
397 #define CONFIG_ARCHITECTURE_FLAGS "-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16"
398 #define CONFIG_ARCHITECTURE_ARMV7_M_KERNEL_BASEPRI 0
399 #undef CONFIG_ARCHITECTURE_ARM_CORTEX_M3
400 #define CONFIG_ARCHITECTURE_ARM_CORTEX_M4
401 #undef CONFIG_ARCHITECTURE_ARM_CORTEX_M4_R0P0
402 #define CONFIG_ARCHITECTURE_ARM_CORTEX_M4_R0P1
403 #undef CONFIG_ARCHITECTURE_ARM_CORTEX_M7
404 #define CONFIG_ARCHITECTURE_ARMV6_M_ARMV7_M_MAIN_STACK_SIZE 1024
405 #define CONFIG_ARCHITECTURE_INCLUDES "source/architecture/ARM/ARMv6-M-ARMv7-M/include"
406 #define CONFIG_ARCHITECTURE_FPU
407 #undef CONFIG_ARCHITECTURE_ASCENDING_STACK
408 #undef CONFIG_ARCHITECTURE_EMPTY_STACK
409 #define CONFIG_ARCHITECTURE_HAS_FPU
410 #define CONFIG_ARCHITECTURE_ARM
411 #define CONFIG_TICK_FREQUENCY 1000
412 #define CONFIG_ROUND_ROBIN_FREQUENCY 10
413 #define CONFIG_THREAD_DETACH_ENABLE
414 #define CONFIG_MAIN_THREAD_STACK_SIZE 4096
415 #define CONFIG_MAIN_THREAD_PRIORITY 127
416 #define CONFIG_MAIN_THREAD_CAN_RECEIVE_SIGNALS
417 #define CONFIG_MAIN_THREAD_QUEUED_SIGNALS 8
418 #define CONFIG_MAIN_THREAD_SIGNAL_ACTIONS 8
419 #define CONFIG_CHECK_FUNCTION_CONTEXT_ENABLE
420 #define CONFIG_CHECK_STACK_POINTER_RANGE_CONTEXT_SWITCH_ENABLE
421 #define CONFIG_CHECK_STACK_POINTER_RANGE_SYSTEM_TICK_ENABLE
422 #define CONFIG_CHECK_STACK_GUARD_CONTEXT_SWITCH_ENABLE
423 #define CONFIG_CHECK_STACK_GUARD_SYSTEM_TICK_ENABLE
424 #define CONFIG_STACK_GUARD_SIZE 32
425 #define CONFIG_TEST_APPLICATION_ENABLE
426 #undef CONFIG_BUILD_OPTIMIZATION_O0
427 #undef CONFIG_BUILD_OPTIMIZATION_O1
428 #define CONFIG_BUILD_OPTIMIZATION_O2
429 #undef CONFIG_BUILD_OPTIMIZATION_O3
430 #undef CONFIG_BUILD_OPTIMIZATION_OS
431 #undef CONFIG_BUILD_OPTIMIZATION_OG
432 #define CONFIG_DEBUGGING_INFORMATION_ENABLE
433 #define CONFIG_ASSERT_ENABLE
434 #undef CONFIG_LDSCRIPT_ROM_SIZE_MANUAL_CONFIGURATION
435 #define CONFIG_LDSCRIPT_ROM_BEGIN 0
436 #define CONFIG_LDSCRIPT_ROM_END 1048576
437 #define CONFIG_BUILD_OPTIMIZATION "-O2"
438 #define CONFIG_DEBUGGING_INFORMATION_COMPILATION "-g -ggdb3"
439 #define CONFIG_DEBUGGING_INFORMATION_LINKING "-g"
440 #define CONFIG_ASSERT ""
441 
442 #endif /* INCLUDE_DISTORTOS_DISTORTOSCONFIGURATION_H_ */