12 #ifndef SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_ 13 #define SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_ 39 #if defined(DISTORTOS_CHIP_STM32F446) || defined(DISTORTOS_CHIP_STM32F469) || defined(DISTORTOS_CHIP_STM32F479) 44 #endif // defined(DISTORTOS_CHIP_STM32F446) || defined(DISTORTOS_CHIP_STM32F469) || defined(DISTORTOS_CHIP_STM32F479) 58 #if defined(DISTORTOS_CHIP_STM32F401) 59 constexpr uint16_t
minPlln {192};
60 #else // !defined(DISTORTOS_CHIP_STM32F401) 62 #endif // !defined(DISTORTOS_CHIP_STM32F401) 73 #if defined(DISTORTOS_CHIP_STM32F412) || defined(DISTORTOS_CHIP_STM32F413) || defined(DISTORTOS_CHIP_STM32F423) || \ 74 defined(DISTORTOS_CHIP_STM32F446) || defined(DISTORTOS_CHIP_STM32F469) || defined(DISTORTOS_CHIP_STM32F479) 77 constexpr uint8_t minPllr {2};
80 constexpr uint8_t maxPllr {7};
82 #endif // defined(DISTORTOS_CHIP_STM32F412) || defined(DISTORTOS_CHIP_STM32F413) || 225 #if defined(DISTORTOS_CHIP_STM32F412) || defined(DISTORTOS_CHIP_STM32F413) || defined(DISTORTOS_CHIP_STM32F423) || \ 226 defined(DISTORTOS_CHIP_STM32F446) || defined(DISTORTOS_CHIP_STM32F469) || defined(DISTORTOS_CHIP_STM32F479) 245 int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq, uint8_t pllr);
247 #else // !defined(DISTORTOS_CHIP_STM32F412) && !defined(DISTORTOS_CHIP_STM32F413) && 267 int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq);
269 #endif // !defined(DISTORTOS_CHIP_STM32F412) && !defined(DISTORTOS_CHIP_STM32F413) && 285 #endif // SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_ void switchSystemClock(SystemClockSource source)
Switches system clock.
Definition: STM32F4-RCC.cpp:151
HSI oscillator selected as system clock.
constexpr uint8_t maxPllm
maximum allowed value for PLLM
Definition: STM32F4-RCC.hpp:55
constexpr uint8_t pllpDiv8
fourth allowed value for PLLP - 8
Definition: STM32F4-RCC.hpp:96
constexpr uint16_t hpreDiv256
eighth allowed value for AHB divider - 256
Definition: STM32F4-RCC.hpp:120
constexpr uint8_t pllpDiv6
third allowed value for PLLP - 6
Definition: STM32F4-RCC.hpp:93
constexpr uint8_t pllpDiv4
second allowed value for PLLP - 4
Definition: STM32F4-RCC.hpp:90
main PLL selected as system clock
void disableHse()
Disables HSE clock.
Definition: STM32F4-RCC.cpp:92
constexpr uint16_t hpreDiv512
ninth allowed value for AHB divider - 512
Definition: STM32F4-RCC.hpp:123
constexpr uint8_t minPllq
minimum allowed value for PLLQ
Definition: STM32F4-RCC.hpp:68
int configurePllInputClockDivider(uint8_t pllm)
Configures divider of PLL input clock (PLLM value) for main and audio PLLs.
Definition: STM32F4-RCC.cpp:83
constexpr uint16_t hpreDiv128
seventh allowed value for AHB divider - 128
Definition: STM32F4-RCC.hpp:117
void disablePll()
Disables main PLL.
Definition: STM32F4-RCC.cpp:97
constexpr uint16_t hpreDiv2
second allowed value for AHB divider - 2
Definition: STM32F4-RCC.hpp:102
constexpr uint8_t minPllm
minimum allowed value for PLLM
Definition: STM32F4-RCC.hpp:52
constexpr uint8_t ppreDiv8
fourth allowed value for APB1 and APB2 dividers - 8
Definition: STM32F4-RCC.hpp:135
constexpr uint8_t maxPllq
maximum allowed value for PLLQ
Definition: STM32F4-RCC.hpp:71
constexpr uint16_t hpreDiv64
sixth allowed value for AHB divider - 64
Definition: STM32F4-RCC.hpp:114
constexpr uint8_t pllpDiv2
first allowed value for PLLP - 2
Definition: STM32F4-RCC.hpp:87
constexpr uint16_t hpreDiv1
first allowed value for AHB divider - 1
Definition: STM32F4-RCC.hpp:99
SystemClockSource
system clock source
Definition: STM32F4-RCC.hpp:30
constexpr uint8_t ppreDiv1
first allowed value for APB1 and APB2 dividers - 1
Definition: STM32F4-RCC.hpp:126
int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq)
Enables main PLL.
Definition: STM32F4-RCC.cpp:115
Top-level namespace of distortos project.
Definition: buttons.hpp:33
constexpr uint16_t minPlln
minimum allowed value for PLLN
Definition: STM32F4-RCC.hpp:61
constexpr uint16_t hpreDiv4
third allowed value for AHB divider - 4
Definition: STM32F4-RCC.hpp:105
int configureApbClockDivider(bool ppre2, uint8_t ppre)
Configures divider of APB1 or APB2 clock (PPRE1 or PPRE2 value).
Definition: STM32F4-RCC.cpp:56
constexpr uint16_t maxPlln
maximum allowed value for PLLN
Definition: STM32F4-RCC.hpp:65
constexpr uint8_t ppreDiv2
second allowed value for APB1 and APB2 dividers - 2
Definition: STM32F4-RCC.hpp:129
constexpr uint16_t hpreDiv16
fifth allowed value for AHB divider - 16
Definition: STM32F4-RCC.hpp:111
HSE oscillator selected as system clock.
int configureAhbClockDivider(uint16_t hpre)
Configures divider of AHB clock (HPRE value).
Definition: STM32F4-RCC.cpp:31
constexpr uint8_t ppreDiv4
third allowed value for APB1 and APB2 dividers - 4
Definition: STM32F4-RCC.hpp:132
void enableHse(bool bypass)
Enables HSE clock.
Definition: STM32F4-RCC.cpp:102
constexpr uint16_t hpreDiv8
fourth allowed value for AHB divider - 8
Definition: STM32F4-RCC.hpp:108
constexpr uint8_t ppreDiv16
fifth allowed value for APB1 and APB2 dividers - 16
Definition: STM32F4-RCC.hpp:138
void configurePllClockSource(bool hse)
Configures clock source of main and audio PLLs.
Definition: STM32F4-RCC.cpp:78