distortos  v0.4.0
object-oriented C++ RTOS for microcontrollers
STM32F4-RCC.hpp
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1 
12 #ifndef SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_
13 #define SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_
14 
16 
17 #include <cstdint>
18 
19 namespace distortos
20 {
21 
22 namespace chip
23 {
24 
25 /*---------------------------------------------------------------------------------------------------------------------+
26 | global types
27 +---------------------------------------------------------------------------------------------------------------------*/
28 
30 enum class SystemClockSource : uint8_t
31 {
33  hsi,
35  hse,
37  pll,
38 
39 #if defined(CONFIG_CHIP_STM32F446) || defined(CONFIG_CHIP_STM32F469) || defined(CONFIG_CHIP_STM32F479)
40 
42  pllr,
43 
44 #endif // defined(CONFIG_CHIP_STM32F446) || defined(CONFIG_CHIP_STM32F469) || defined(CONFIG_CHIP_STM32F479)
45 };
46 
47 /*---------------------------------------------------------------------------------------------------------------------+
48 | global constants
49 +---------------------------------------------------------------------------------------------------------------------*/
50 
52 constexpr uint8_t minPllm {2};
53 
55 constexpr uint8_t maxPllm {63};
56 
58 #if defined(CONFIG_CHIP_STM32F401)
59 constexpr uint16_t minPlln {192};
60 #else // !defined(CONFIG_CHIP_STM32F401)
61 constexpr uint16_t minPlln {50};
62 #endif // !defined(CONFIG_CHIP_STM32F401)
63 
65 constexpr uint16_t maxPlln {432};
66 
68 constexpr uint8_t minPllq {2};
69 
71 constexpr uint8_t maxPllq {15};
72 
73 #if defined(CONFIG_CHIP_STM32F412) || defined(CONFIG_CHIP_STM32F413) || defined(CONFIG_CHIP_STM32F423) || \
74  defined(CONFIG_CHIP_STM32F446) || defined(CONFIG_CHIP_STM32F469) || defined(CONFIG_CHIP_STM32F479)
75 
77 constexpr uint8_t minPllr {2};
78 
80 constexpr uint8_t maxPllr {7};
81 
82 #endif // defined(CONFIG_CHIP_STM32F412) || defined(CONFIG_CHIP_STM32F413) || defined(CONFIG_CHIP_STM32F423) ||
83  // defined(CONFIG_CHIP_STM32F446) || defined(CONFIG_CHIP_STM32F469) || defined(CONFIG_CHIP_STM32F479)
84 
86 constexpr uint8_t pllpDiv2 {2};
87 
89 constexpr uint8_t pllpDiv4 {4};
90 
92 constexpr uint8_t pllpDiv6 {6};
93 
95 constexpr uint8_t pllpDiv8 {8};
96 
98 constexpr uint16_t hpreDiv1 {1};
99 
101 constexpr uint16_t hpreDiv2 {2};
102 
104 constexpr uint16_t hpreDiv4 {4};
105 
107 constexpr uint16_t hpreDiv8 {8};
108 
110 constexpr uint16_t hpreDiv16 {16};
111 
113 constexpr uint16_t hpreDiv64 {64};
114 
116 constexpr uint16_t hpreDiv128 {128};
117 
119 constexpr uint16_t hpreDiv256 {256};
120 
122 constexpr uint16_t hpreDiv512 {512};
123 
125 constexpr uint8_t ppreDiv1 {1};
126 
128 constexpr uint8_t ppreDiv2 {2};
129 
131 constexpr uint8_t ppreDiv4 {4};
132 
134 constexpr uint8_t ppreDiv8 {8};
135 
137 constexpr uint8_t ppreDiv16 {16};
138 
139 /*---------------------------------------------------------------------------------------------------------------------+
140 | global functions' declarations
141 +---------------------------------------------------------------------------------------------------------------------*/
142 
153 int configureAhbClockDivider(uint16_t hpre);
154 
165 int configureApbClockDivider(bool ppre2, uint8_t ppre);
166 
176 void configurePllClockSource(bool hse);
177 
190 int configurePllInputClockDivider(uint8_t pllm);
191 
199 void disableHse();
200 
208 void disablePll();
209 
222 void enableHse(bool bypass);
223 
224 #if defined(CONFIG_CHIP_STM32F412) || defined(CONFIG_CHIP_STM32F413) || defined(CONFIG_CHIP_STM32F423) || \
225  defined(CONFIG_CHIP_STM32F446) || defined(CONFIG_CHIP_STM32F469) || defined(CONFIG_CHIP_STM32F479)
226 
244 int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq, uint8_t pllr);
245 
246 #else // !defined(CONFIG_CHIP_STM32F412) && !defined(CONFIG_CHIP_STM32F413) && !defined(CONFIG_CHIP_STM32F423) &&
247  // !defined(CONFIG_CHIP_STM32F446) && !defined(CONFIG_CHIP_STM32F469) && !defined(CONFIG_CHIP_STM32F479)
248 
265 int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq);
266 
267 #endif // !defined(CONFIG_CHIP_STM32F412) && !defined(CONFIG_CHIP_STM32F413) && !defined(CONFIG_CHIP_STM32F423) &&
268  // !defined(CONFIG_CHIP_STM32F446) && !defined(CONFIG_CHIP_STM32F469) && !defined(CONFIG_CHIP_STM32F479)
269 
277 
278 } // namespace chip
279 
280 } // namespace distortos
281 
282 #endif // SOURCE_CHIP_STM32_STM32F4_INCLUDE_DISTORTOS_CHIP_STM32F4_RCC_HPP_
void switchSystemClock(SystemClockSource source)
Switches system clock.
Definition: STM32F4-RCC.cpp:147
HSI oscillator selected as system clock.
constexpr uint8_t maxPllm
maximum allowed value for PLLM
Definition: STM32F4-RCC.hpp:55
constexpr uint8_t pllpDiv8
fourth allowed value for PLLP - 8
Definition: STM32F4-RCC.hpp:95
constexpr uint16_t hpreDiv256
eighth allowed value for AHB divider - 256
Definition: STM32F4-RCC.hpp:119
constexpr uint8_t pllpDiv6
third allowed value for PLLP - 6
Definition: STM32F4-RCC.hpp:92
constexpr uint8_t pllpDiv4
second allowed value for PLLP - 4
Definition: STM32F4-RCC.hpp:89
main PLL selected as system clock
void disableHse()
Disables HSE clock.
Definition: STM32F4-RCC.cpp:92
constexpr uint16_t hpreDiv512
ninth allowed value for AHB divider - 512
Definition: STM32F4-RCC.hpp:122
constexpr uint8_t minPllq
minimum allowed value for PLLQ
Definition: STM32F4-RCC.hpp:68
int configurePllInputClockDivider(uint8_t pllm)
Configures divider of PLL input clock (PLLM value) for main and audio PLLs.
Definition: STM32F4-RCC.cpp:83
constexpr uint16_t hpreDiv128
seventh allowed value for AHB divider - 128
Definition: STM32F4-RCC.hpp:116
void disablePll()
Disables main PLL.
Definition: STM32F4-RCC.cpp:97
constexpr uint16_t hpreDiv2
second allowed value for AHB divider - 2
Definition: STM32F4-RCC.hpp:101
constexpr uint8_t minPllm
minimum allowed value for PLLM
Definition: STM32F4-RCC.hpp:52
constexpr uint8_t ppreDiv8
fourth allowed value for APB1 and APB2 dividers - 8
Definition: STM32F4-RCC.hpp:134
constexpr uint8_t maxPllq
maximum allowed value for PLLQ
Definition: STM32F4-RCC.hpp:71
constexpr uint16_t hpreDiv64
sixth allowed value for AHB divider - 64
Definition: STM32F4-RCC.hpp:113
constexpr uint8_t pllpDiv2
first allowed value for PLLP - 2
Definition: STM32F4-RCC.hpp:86
constexpr uint16_t hpreDiv1
first allowed value for AHB divider - 1
Definition: STM32F4-RCC.hpp:98
distortos configuration
SystemClockSource
system clock source
Definition: STM32F4-RCC.hpp:30
constexpr uint8_t ppreDiv1
first allowed value for APB1 and APB2 dividers - 1
Definition: STM32F4-RCC.hpp:125
int enablePll(uint16_t plln, uint8_t pllp, uint8_t pllq)
Enables main PLL.
Definition: STM32F4-RCC.cpp:114
Top-level namespace of distortos project.
constexpr uint16_t minPlln
minimum allowed value for PLLN
Definition: STM32F4-RCC.hpp:61
constexpr uint16_t hpreDiv4
third allowed value for AHB divider - 4
Definition: STM32F4-RCC.hpp:104
int configureApbClockDivider(bool ppre2, uint8_t ppre)
Configures divider of APB1 or APB2 clock (PPRE1 or PPRE2 value).
Definition: STM32F4-RCC.cpp:56
constexpr uint16_t maxPlln
maximum allowed value for PLLN
Definition: STM32F4-RCC.hpp:65
constexpr uint8_t ppreDiv2
second allowed value for APB1 and APB2 dividers - 2
Definition: STM32F4-RCC.hpp:128
constexpr uint16_t hpreDiv16
fifth allowed value for AHB divider - 16
Definition: STM32F4-RCC.hpp:110
HSE oscillator selected as system clock.
int configureAhbClockDivider(uint16_t hpre)
Configures divider of AHB clock (HPRE value).
Definition: STM32F4-RCC.cpp:31
constexpr uint8_t ppreDiv4
third allowed value for APB1 and APB2 dividers - 4
Definition: STM32F4-RCC.hpp:131
void enableHse(bool bypass)
Enables HSE clock.
Definition: STM32F4-RCC.cpp:102
constexpr uint16_t hpreDiv8
fourth allowed value for AHB divider - 8
Definition: STM32F4-RCC.hpp:107
constexpr uint8_t ppreDiv16
fifth allowed value for APB1 and APB2 dividers - 16
Definition: STM32F4-RCC.hpp:137
void configurePllClockSource(bool hse)
Configures clock source of main and audio PLLs.
Definition: STM32F4-RCC.cpp:78